1. Field of the Invention
The present invention relates to dynamic random access storage memory circuits, and more particularly to improved precharge and input/output operation for power savings in random access memories.
2. Description of the Prior Art
U.S. Pat. No. 4,387,449 issued Jan. 7, 1983 to Masuda, entitled PROGRAMMABLE MEMORY DEVICE HAVING REDUCED POWER CONSUMPTION UPON UNSELECTION, discloses a memory device capable of operating in a power down mode in which peripheral memory circuitry is inactivated, the power down mode being assumed in response to an unselect signal at any one of a plurality of chip enable terminals. In response to a write potential at the output terminal of the memory, a detector circuit will leave the output circuit inactivated but will activate any peripheral circuitry necessary for the write operation.
U.S. Pat. No. 4,405,996 issued Sep. 20, 1983 to Stewart, entitled PRECHARGE WITH POWER CONSERVATION, describes a circuit having a "selected" and a "deselected" state and a controllable pulse generating network which is operable when the circuit is "selected". The latch senses and stores a signal evidencing a change of state of any one of certain input signals to the circuit when the circuit deselected. The pulse network is responsive to the stored signal and produces a pulse, indicative of the occurrence of a change when the circuit is subsequently selected.
U.S. Pat. No. 4,409,679 issued Oct. 11, 1983 to Kurafuji et al, entitled STATIC MEMORY CIRCUIT, discloses a static memory circuit incorporating memory cells of a MOS static type comprising a plurality of potential setting circuits for setting the ground side potential of one selected memory cell to be lower than those of other non-selected memory cells. Thus, reducing power dissipation by reducing current flowing through half-selected and non-selected memory cells without reducing read speed.
U.S. Pat. No. 4,528,646 issued Jul. 9, 1985 to Ochii et al, entitled SEMICONDUCTOR MEMORY WITH SELECTIVELY ENABLED PRECHARGE AND SENSE AMPLIFIER CIRCUITS, discloses bit line precharge circuits, sense AMP circuits and input-output line precharge circuits which are respectively divided into two groups by select circuits which are controlled by a select control signal. Only the selected precharge circuits and the sense AMP circuits are enabled before a readout operation. The peak current for precharging bit lines is reduced to one-half as compared to conventional circuits due to the decrease of stray capacitance to be precharged.
U.S. Pat. No. 4,561,070 issued Dec. 24, 1985 to Armstrong, entitled INTEGRATED CIRCUIT MEMORY, discloses an integrated circuit memory wherein an array of memory elements is addressed by a decoder circuit responding to an address signal. The decoder circuit includes a plurality of sections, each one thereof being used to address a different section of the array. A decoder section selector is provided which, in response to the addressing signal, determines the section of the array being addressed and electrically couples the one of the plurality of decoder circuit sections which is coupled to such addressed array section to a power source while electrically decoupling the remaining section of the decoder circuit from such power source. With such arrangement, only a portion of the decoder circuit is electrically coupled to the power source when addressing the array thereby reducing the power consumption of the integrated circuit memory.
U.S. Pat. 4,570,243 issued Feb. 11, 1986 to Sud et al, entitled LOW POWER I/O SCHEME FOR SEMICONDUCTOR MEMORIES, describes a low power I/O scheme which is particularly useful in wide word semiconductor memories which include redundant memory cells as well as regular memory cells. Conventional load transistors for a main data bus are turned off during all write operations to conserve power. In addition, predata lines which carry data between memory cells and the main data bus include load transistors that are turned off during normal read or write operations to conserve additional power, and turned on during spare read or write operations to preserve the stability of unselected regular cells. The predata lines are held above ground potential during read or write operations to prevent conduction of deselected column select transistors.
U.S. Pat. No. 4,616,342 issued Oct. 7, 1986 to Miyamoto, entitled SEMICONDUCTOR MEMORY DEVICE, discloses a semiconductor memory device that comprises word lines connected to a row of memory cells, pairs of bit lines each connected to a different column of memory cells, word line drive means for driving the word line, and data sensing means. The word line drive means drives a selected word line only during a predetermined time duration which is shorter than the time duration of a word selection signal. The data sensing means includes a differential amplifier including a pair of bipolar transistors connected at their base electrodes to a pair of bit lines. Within the predetermined shorter time period, the differential amplifier senses the data stored in a selected memory cell and that sensed data is latched by a latching circuit.
U.S. Pat. No. 4,751,683 issued Jan. 14, 1988 to Wada et al, entitled STATIC SEMICONDUCTOR MEMORY DEVICE COMPRISING WORD LINES EACH OPERATING AT THREE DIFFERENT VOLTAGE LEVELS, describes a semiconductor memory device that operates in response to an address transition detection (ATD) signal for detecting a change in an x address as well as to a write enable signal WE to make the signal on a selected word line vary according to the read mode and the write mode, whereby dissipation of electric power can be reduced.
U.S. Pat. No. 4,760,562 issued Jul. 26, 1988 to Ohtani, entitled MOS STATIC MEMORY CIRCUIT, discloses voltage converters arranged in units of columns in a memory device. Each voltage converter is connected to a column decoder. The column decoder receives a column address signal and supplies a column selection signal to the voltage converter. The voltage converters apply a ground level voltage to the source junctions of the drive transistor pairs of the memory cells of the selected columns, and a voltage higher than the ground level voltage to the source junctions of the drive transistor pairs of the memory cells of the non-selected columns so as to decrease power consumption in the non-selected columns as compared with that in the selected columns.